Jaehwan (John) Lee, Ph.D.

Assistant Professor

I am looking for potential licensees for my recently filed patents

Abstract: The invented hardware deadlock detection scheme utilizes a resource allocation graph representation, which is implemented using combinational logic. This hardware can be used for multi-unit resource systems, as well as single-unit resource systems. The host computer system informs this hardware of all resource allocation events, and upon each resource event, this hardware detect deadlock instantaneously if it occurs, which can be used by the system to resolve deadlock immediately. Note: Deadlock is a situation in which two or more processes competing for resources are waiting for the others to finish, and neither ever does. For example, deadlock occurs when a first process holding a first resource waits for a second resource that is being held by a second process, which is waiting for the first resource. In this scenario, because neither process can acquire all resources it needs to proceed, both processes are blocked permanently. Unless this situation is detected and alleviated, the system remains deadlocked.

Automatic Generation of Multithreaded Uniprocessor and Multiprocessor Simulators

Constructing a quality simulator requires tremendous efforts. Moreover, modifying an already built simulator to use to explore various characteristics of the components of the simulator is also non-trivial task and typically time-consuming and error-prone. To overcome this drawback, researchers have invented Architecture Description Language (ADL) that can be used to specify instruction set architecture. ADL is typically designed to have simple syntax and thus easier to understand, which enables not only to easily build a computer simulator and its tool suite but also to easily modify and explore design space of the modeled system. Furthermore, ADL enables users to automatically generate different simulators with different parameters and components.

Lack of educational computer architecture simulators in the academia hinders learning process of EE, ECE and CS students in computer architecture. Overcoming such impediment requires good modularized visually enhanced computer architecture simulators that demonstrate how critical components of processors operate. Such components are MIPS pipeline, scoreboarding, tomasulo and superscalar structures, shown in popular computer organization books. To help students grasp such topics easier, we develop an educational instruction set simulator with visualization using a recent new programming language C#.

Multithreaded Full System Simulator for Hybrid Systems with Multiprocessors and FPGAs

Implementing a full system simulator for hybrid systems with multicore processors and FPGAs.

Reconfigurable Logic Assisted Parallel Main Memory Database System for Query Intensive Application

Reconfigurable Logic (RL) coprocessors such as FPGAs are commodity hardware accelerators that show significant promise in accelerating computation. However, these coprocessors have not been explored comprehensively within database research. Our group's long-term vision is to provide a comprehensive and demonstrative approach to integrate and use RL coprocessors as database accelerators in fast, extensible reconfigurable logic assisted database management systems.

Codesign is a process in which you use similar methods and sets of connected tools and languages, for both hardware and software design. Codesign helps shorten development time by enabling the concurrent development of hardware and software, and by allowing software to be developed on “virtual hardware platforms” before the final hardware is ready. In addition, a top-down approach enhances your ability to analyze and tackle system partitioning and verification by enabling you to explore the design space fully.

Our hardware implementation of a software algorithm is a fully hardware oriented implementation exploiting maximum hardware parallelism of all computations of the original algorithm. This methodology reduces not only algorithm execution time but also the run-time complexity.
Past designs: O(1) Deadlock Detection Hardware, O(min(m,n)) Dealock Detection Hwardware, Deadlock detection and avoidance hardware, Parallel Banker's Algorithm in hardware

System designers use the specification and their experience to make expert's guesses on the performance of the system. Based on these guesses, they decide which part of the system will be implemented in hardware and which part in software. This step is called partitioning. It also involves writing the behavioral description for the different parts of the system. The hardware part, for example, may be described using VHDL or Verilog and the software model using the C language. In addition, the interfacing logic, including any handshaking or bus logic, is also decided at this time. This kind of partitioning methodology applied to the real-time operating system (RTOS) is hardware/software partitioning of RTOS. Our research in this methodology is how to reduce time on design and verification, overcome sub-optimal design, and finally improve quality of design.
Past Designs: Hardware/Software RTOS partitioning framework for multiprocessor system on a chip.

Technology trends show that many future system-on-chips will include multiple processors from two to tens or even hundreds including heterogeneous processors in many cases. There are many challenges and problems including what we don't know yet.
Past designs: Four PowerPC 755 SMP architecture, Four ARM9TDMI SMP architecture

Design and implementation of various kinds of embedded systems, from home and commercial, to industry and military.
Past designs: The designs accomplished during my work in Agency for Defense Development.

Dissertation: Hardware-oriented Parallel Deadlock Detection Algorithms with Reduced Run-time Complexity

Ph.D., Electrical and Computer Engineering, Georgia Tech, Atlanta, GA, 2004
M.S., Electrical and Computer Engineering, Georgia Tech, Atlanta, GA, 2003
B.S., School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Korea