Jaehwan (John) Lee, Ph.D.

Assistant Professor

Current Projects

NSF-CCF-0811448: Development of Parallel Reduced Run-Time Complexity Hardware-Oriented Deadlock Algorithms with Proofs and Extensions to Other Areas

This research investigates novel techniques to inherently equip multiprocessor system-on-chips with a hardware mechanism that can detect deadlocks instantly so that OS can react in minimal time. The central idea behind its methodology is to transform one form of complexity (e.g., graph) into another form of complexity (e.g., matrix) that can then be parallelized in hardware. This project develops various parallel hardware-oriented deadlock detection algorithms and their variations, which will be not only faster but will also dramatically reduce the run-time complexity from at most linear down to constant (i.e., O(1)). The research is of significant value to the reliability of many real-time systems such as medical robots, automobiles, and avionics. Finally, this project extends devised data structures and algorithms to potential algorithms in various other areas that utilize corresponding graph oriented data structures.
Outcomes

O(log(min(m,n))) Parallel Dealock Detection Algorithm and Its Hardware with O(1) detection for Multi-Unit Resource Systems
O(1) Parallel Dealock Detection Algorithm and Its Hardware for Single-Unit Resource Systems
Instant Deadlock Detection Hardware for Multi-Unit Resource Systems
O(L) Parallel Shortest Path Algorithm and Its Hardware Implementation
O(n) Parallel Shortest Path Algorithm and Its Hardware Implementation

NSF-CNS-EHS-0834682: Development of SYMBIOTE, A Reconfigurable Logic Assisted Data Stream Management System for Multimedia Sensor Networks

This research investigates a novel class of Data Stream Management Systems (DSMSs) called Reconfigurable Logic Assisted DSMS (RLADSMS) with a demonstrative prototype called SYMBIOTE for real-time processing of high bandwidth multimedia data streams in a computer vision based traffic monitoring system. To utilize hardware-friendly decomposed storage model, this project provides two query operators (namely, Split-choose and Merge operators), one macro-operator called Split-merge, and a library of reusable, parameterizable, reduced run-time, and reduced spatial complexity hardware DSMS operators, such as Filter, Map, Union, Bsort, Aggregate, and Join. Furthermore, the project investigates hardware implementations of approximate query answering techniques for sliding windows; landmark windows; and sketches, random sampling and wavelets.
Outcomes

IUPUI-RSFG: Development of a Framework for Dynamically Configurable Visually Enhanced Computer Architecture Simulation

The long-term goal of this research is to provide computer architecture students and researchers with a comprehensible, modifiable, and configurable simulator versatile enough for quickly realizing and validating new ideas and learning existing concepts. The specific objective is to investigate several innovative approaches for creating a novel framework for automatic generation of computer architecture simulators. This project will deliver a highly visual, dynamically configurable, simulator generation framework for computer architecture research and education utilizing new techniques and expertise gained during prior research. The innovative approaches include ample functionality, extreme flexibility, on-the-fly dynamicity, enhanced-visuality, and clear modularity.

IUPUI-RSFG: Automatic Generation of Multithreaded Uniprocessor and Multiprocessor Simulators

Constructing a quality simulator requires tremendous efforts. Moreover, modifying an already built simulator to use to explore various characteristics of the components of the simulator is also non-trivial task and typically time-consuming and error-prone. To overcome this drawback, researchers have invented Architecture Description Language (ADL) that can be used to specify instruction set architecture. ADL is typically designed to have simple syntax and thus easier to understand, which enables not only to easily build a computer simulator and its tool suite but also to easily modify and explore design space of the modeled system. Furthermore, ADL enables users to automatically generate different simulators with different parameters and components.
Outcomes

An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators

Multithreaded Full System Simulator for Hybrid Systems with Multiprocessors and FPGAs

Implementing a full system simulator for hybrid systems with multicore processors and FPGAs.

Reconfigurable Logic Assisted Parallel Main Memory Database System for Query Intensive Application

Reconfigurable Logic (RL) coprocessors such as FPGAs are commodity hardware accelerators that show significant promise in accelerating computation. However, these coprocessors have not been explored comprehensively within database research. Our group's long-term vision is to provide a comprehensive and demonstrative approach to integrate and use RL coprocessors as database accelerators in fast, extensible reconfigurable logic assisted database management systems.