Jaehwan (John) Lee, Ph.D.

Assistant Professor

Department of Electrical and Computer Engineering
Purdue School of Engineering and Technology
Indiana University-Purdue University Indianapolis
723 West Michigan St. SL 160, Indianapolis, IN 46202-5132
Tel: 317-278-2267, Fax: 317-274-4493, Email: johnlee at iupui.edu

Publications

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Journal Articles

Xiang Xiao and J. Lee, "A True O(1) Parallel Deadlock Detection Algorithm for Single-unit Resource Systems and Its Hardware Implementation," IEEE Transactions on Parallel and Distributed Systems, 21(1), pp. 4-19, Jan. 2010.
P. Vaidya and J. Lee, "Multiprocessor simulation using communicating sequential processes," International Journal of Computer Aided Engineering and Technology (IJCAET), 2(1), pp. ??-??, 2010.
C. Barnes, P. Vaidya and J. Lee, "An XML-Based ADL Framework for Automatic Generation of Multithreaded Computer Architecture Simulators," IEEE Computer Architecture Letters, 8(1), pp. 13-16, Jan-Jun 2009.
J. Lee and Xiang Xiao, "A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time Complexity," IEEE Computer Architecture Letters, 7(2), pp. 45-48, Jul-Dec 2008.
Xiang Xiao and J. Lee, "A Novel O(1) Deadlock Detection Methodology for Multi-unit Resource Systems and Its Hardware Implementation on Multiprocessor System-on-Chip," IEEE Transactions on Parallel and Distributed Systems, 19(12), pp.1657-1670, Dec. 2008.
Xiang Xiao and J. Lee, "A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip," IEEE Computer Architecture Letters, 6(2), pp. 41-44, Jul-Dec 2007.
J. Lee and V. Mooney, "A Novel O(n) Parallel Banker's Algorithm for System-on-a-Chip," IEEE Transactions on Parallel and Distributed Systems, 17(12), pp. 1377-1389, Dec. 2006.
J. Lee and V. Mooney, "An O(min(m,n)) Parallel Deadlock Detection Algorithm," ACM Transactions on Design Automation of Electronic Systems, 10(3), pp.573-586, July 2005. ACM TODAES, Article, and What I hoped to publish
J. Lee and V. Mooney, "Hardware/Software Partitioning of Operating Systems: Focus on Deadlock Detection and Avoidance," IEE Transactions on Computers and Digital Techniques, 152(2), pp.167-182, March 2005. IEE CDT Draft

Book Chapters

J. Lee and V. Mooney, "Hardware/Software Partitioning of Operating Systems: Focus on Deadlock Avoidance," Chapter 4 of System On Chip: Next Generation Electronics, edited by B. Al-Hashimi, pp.121-160, IEE, UK, Jan. 2006, ISBN: 0-86341-552-0 & 978-086341-552-4. Draft

Conference Proceedings

Pranav Vaidya and J. Lee, "A novel multicontext coarse-grained join accelerator for column-oriented databases", International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 158-164, July 2009, Presentation (pdf)
Tuo Shi and J. Lee, "An O(L) Parallel Shortest Path Algorithm," International Conference on Computer Design (CDES), pp. 119-124, July 2009, Presentation (pdf)
Pranav Vaidya, J. Lee and Xiang Xiao, "Characterization of TPC-H Queries for a Column-Oriented Database on a Dual-Core AMD Athlon Processor," ACM 17th Conference on Information and Knowledge Management (CIKM), pp. 1411-1412, Oct. 2008.
Xiang Xiao, Tuo Shi, Pranav Vaidya and J. Lee, "R-Tree: A Hardware Implementation," International Conference on Computer Design (CDES), pp. 3-9, July 2008.
Xiang Xiao and J. Lee, "Main Memory DBMS on Modern Processors, a Scalable Approach for Database Performance Characterization Using Simulation," International Workshop on Scalable Data Management Applications and Systems (SDMAS), International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), pp. 617-623, July 2008.
Pranav Vaidya, Xiang Xiao and J. Lee, "Multiprocessor Simulation Using Communicating Sequential Processes," International Conference on Modeling, Simulation and Visualization Methods (MSV), pp. 215-221, July 2008.
Xiang Xiao and J. Lee, "A Novel Parallel Deadlock Detection Algorithm and Architecture for Multi-unit Resource Systems," IEEE International Conference on Computer Design (ICCD), pp. 480-487, Oct. 2007.
Pranav Vaidya and J. Lee, "Simulation of Hybrid Computer Architectures: Simulators, Methodologies and Recommendations," IFIP-VLSI-SoC 2007, pp. 157-162, Oct. 2007.
Pranav Vaidya and J. Lee, "Design Space Exploration of Multiprocessor Systems with Multicontext Reconfigurable Co-processors", Distinguished Paper, International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), pp. 51-60, June 2007, Presentation (pdf)
J. Lee and V. Mooney, "A Novel O(n) Parallel Banker's Algorithm for System-on-a-Chip," ASPDAC 2005, pp.1304-1308, Jan. 2005, Presentation (pdf)
J. Lee and V. Mooney, "A Novel Deadlock Avoidance Algorithm and Its Hardware Implementation," International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'04), pp.200-205, Sep. 2004, Presentation (pdf)
J. Lee and V. Mooney, "An O(min(m,n)) Parallel Deadlock Detection Algorithm," Tech. Rep. GIT-CC-03-41, Sep. 2003.
J. Lee, V. Mooney, A. Daleby, K. Ingstrom, T. Klevin and L. Lindh, "A comparison of the RTU hardware RTOS with a Hardware/Software RTOS," ASPDAC 2003, pp.683-688, Jan. 2003, Presentation (pdf), was a Best Paper Candidate.
J. Lee, K. Ryu and V. Mooney, "A framework for automatic generation of configuration files for a custom RTOS," ERSA 2002, pp. 31-37, June 2002, Presentation (pdf).
B. S. Akgul, J. Lee and V. Mooney, "System-on-a-chip processor synchronization hardware unit with task preemption support," CASES 2001, pp. 149-157, Nov. 2001, Presentation (pdf).

Dissertation

J. Lee, "Hardware/Software Deadlock Avoidance for Multiprocessor Multiresource System-on-a-Chip," Ph.D. dissertation, Georgia Institute of Technology, Atlanta, Fall 2004. Also available at http://etd.gatech.edu/theses/available/etd-11222004-083429/ Presentation (pdf)